Difference between revisions of "Fundamental Limits"

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{{Chapter
 
{{Chapter
 
|Chapter number=14
 
|Chapter number=14
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|Short name=limits
 
|Previous chapter=Robust Performance
 
|Previous chapter=Robust Performance
 
|Next chapter=Architecture and System Design
 
|Next chapter=Architecture and System Design
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|First edition URL=None
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|Chapter summary=In this chapter we discuss properties that limit performance and robustness of control systems. Non-minimum phase dynamics, due to time delays and right half- plane poles and zeros impose severe limits. There are also nonlinear behaviors that appear at large and small signal levels. Large signal limits can be caused by limited rate and power of actuators, or by constraints required to protect the process. Small signal limits can be caused by measurement noise, friction, and quantization in converters. We also discuss consequences of the limits for loop shaping, and give rules for pole placement design.
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|Chapter contents=# System Design Considerations
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#* Stabilizability and Strong Stabilizability
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#* Right Half-Plane Zeros and Time Delays
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# Bode's Integral Formula
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#* Derivation of Bode's Integral Formula
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# Gain Crossover Frequency Inequality
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# The Maximum Modulus Principle
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# Robust Pole Placement
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#* Fast Stable Process Poles
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#* Slow Stable Process Zeros
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#* Design Rules for Robust Pole Placement
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# Nonlinear Effects
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#* Actuation Limits
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#* Measurement Noise and Friction
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# Further Reading
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:: Exercises
 
}}
 
}}
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{{chapter footer}}

Latest revision as of 05:59, 9 October 2021

Prev: Robust Performance Chapter 14 - Fundamental Limits Next: Architecture and System Design

In this chapter we discuss properties that limit performance and robustness of control systems. Non-minimum phase dynamics, due to time delays and right half- plane poles and zeros impose severe limits. There are also nonlinear behaviors that appear at large and small signal levels. Large signal limits can be caused by limited rate and power of actuators, or by constraints required to protect the process. Small signal limits can be caused by measurement noise, friction, and quantization in converters. We also discuss consequences of the limits for loop shaping, and give rules for pole placement design.

Chapter contents

PDF (24 Jul 2020)

  1. System Design Considerations
    • Stabilizability and Strong Stabilizability
    • Right Half-Plane Zeros and Time Delays
  2. Bode's Integral Formula
    • Derivation of Bode's Integral Formula
  3. Gain Crossover Frequency Inequality
  4. The Maximum Modulus Principle
  5. Robust Pole Placement
    • Fast Stable Process Poles
    • Slow Stable Process Zeros
    • Design Rules for Robust Pole Placement
  6. Nonlinear Effects
    • Actuation Limits
    • Measurement Noise and Friction
  7. Further Reading
Exercises

Teaching Materials

Supplemental Information



Additional Exercises

The following exercises cover some of the topics introduced in this chapter. Exercises marked with a * appear in the printed text.


Frequently Asked Questions

Errata

Python Code

The following Python scripts are available for producing figures that appear in this chapter.


See the software page for more information on how to run these scripts.

Additional Information